In a patent document 1 as a conventional technique, an operation of a circuit is simulated, and a parameter of the circuit (gate width and gate length) is optimized based on information of difference between the simulated value and a target value, thereby optimizing the operation of the circuit.
In patent documents 2 and 3, a parameter (gate width and gate length) of a circuit is optimized based on operation point characteristics of a MOS transistor of a semiconductor circuit, thereby optimizing the operation of the circuit.
In patent documents 4 and 5, a parameter (gate width and gate length) is converted based on an equivalent conversion rule 1.
[Patent Document 1]
Japanese Patent Application Laid-open No. H08-123850
[Patent Document 2]
Japanese Patent Application Laid-open No. H10-112506
[Patent Document 3]
Japanese Patent Application Laid-open No. H11-85822
[Patent Document 4]
Japanese Patent Application Laid-open No.2000-29927
[Patent Document 5]
Japanese Patent No.3315391
In the conventional techniques, a circuit parameter (gate width and gate length) is optimized using means such as a difference, a transistor region or an equivalent conversion rule. Any of them can optimize the circuit parameter (gate width and gate length) of a single transistor in the circuit, but there is a problem that the circuit characteristics can not be optimized only by optimizing the single transistor.
On the other hand, it is possible to optimize the entire circuit by improving an optimizing algorithm, but if the circuit parameter (gate width and gate length) of the single transistor is not optimized, there is a problem that it takes time to optimize the circuit or a result that a designer requires can not be obtained. Especially when a process is change, it takes time to convert all the parameters in to variables in a circuit diagram. Therefore, there are problems that a portion which must be adjusted is generated other than a portion which was converted into a variable due to difference of transistor characteristics, that topology of the original integrated circuit can not be changed, that although simulation for optimization requires great time and this is not practical, a good result can not be obtained, that a result of an appropriate circuit parameter can not be obtained, that since a halfway result must be left when the procedure was suspended halfway while the optimization was being carried out, the optimization must be carried out from the beginning when the optimization is again carried out, that kinds of target performance in the optimization are limited, that there are too many parameters to be set and the operability is poor, that since the optimization is totally carried out automatically, a designer can not be involved in the operation during the optimization, that since the procedure and steps of the optimization are determined for every circuit model, there are many unnecessary optimization procedures, and that the procedure and steps of the optimization can not be saved for every circuit.
It is an object of the present invention to provide a method, an apparatus and a program having high optimization precision and capable of obtaining an answer required by a designer in a short time by combining optimization between individual transistors and optimization as the entire circuit, or by appropriately combining judgment of an operation region, an analysis of the operation region and a SWEEP sensitivity analysis when the optimization is carried out.